The present invention relates to memory systems in which addressable memory locations are organized into blocks and, specifically, to a system employing blocks having different sizes.
Traditionally, memory systems for storing data chunks of varying lengths (e.g. packets, Ethernet frames or fibre channel frames) are organized into blocks. The blocks typically have a common size to simplify the process by which the blocks are allocated and deallocated. The simplest solution would be to define a block size corresponding to the minimum length of a data chunk that is expected to be received. For example, for Ethernet frames that typically vary from 64-1518 bytes, a memory system may define a block size to be 64 bytes long and distribute larger frames across multiple blocks. Unfortunately, the act of addressing a new block, which occurs when a data read operation advances from one block to the next, has its own cost. Therefore, the inefficiency of distributing large data chunks across small blocks can result in lowered performance. Alternatively, one might define a block size to be the largest expected frame size or an intermediate frame size. However, use of blocks with such large granularities incurs waste as an allocated block may be only partially used.
Based upon these performance disadvantages, the inventor determined that there is a need in the art for a memory using blocks of at least two sizes.